Field of the Disclosure
Aspects of the disclosure relate to reset conditions for electrical apparatus. More specifically, aspects relate to electrical designs and methods that allow relaxation of a reset recovery and for removal of timing paths for resets at fast clock speeds.
Description of the Related Art
Performing resets of electrical components can be a complicated process that must be designed by system architects. In memory systems, differing configurations can lead to complicated electrical arrangements to perform required operations. Such memory systems often use “latch” type arrangements which include differing flip-flop electrical arrangements.
FIG. 1 provides a typical reset arrangement 100 for a conventional electrical apparatus that illustrates a relationship between a reset generator 20 to two (2) flip-flops 40, 50. A clock source 10 is connected to the reset generator 20. The output Q 30 of reset generator 20 is connected to the reset point 45 of flip-flop 40 and reset point 55 of flip-flop 50. With this configuration, a reset command placed at the reset generator 20 travels along pathway 65 and then splits into branches 65(1) and 65(2). The distance along pathway 65(1) is different than pathway 65(2), therefore electrical signals sent from the reset generator 20 to each of flip-flop 40 and flip-flop 50 will arrive at the reset points 45, 55 at different times.
Reset operations should be accomplished during a single cycle for the computer system to have proper and predictable operational parameters after the single cycle has ended. The example configuration provided in FIG. 1 illustrates that the different positions of flip-flops 40, 50 cause signals to be received at different times. It can thus be a challenge, therefore, to have the signals received and acted upon within one clock cycle. The problem becomes more manifest the larger the number of flip-flops that are to be reset from the same reset generator.
For many systems, the computer architecture is built onto a single chip and are often called a system on chip (“SOC”) architecture. For SOC systems, the number of flip-flops may easily exceed over 60,000 units. As can be appreciated, large numbers of flip-flop units can greatly increase the overall complexity and potential error from a simple reset. Computer architectures may also be configured to link several different chips together, such that the number of flip-flop units can greatly increase over the previously stated amounts, causing further difficulty during operations.
Referring to FIG. 2, a graph 200 of a conventional hypothetical clock source is illustrated for the embodiment provided in FIG. 1. The amount of time that is required from the activation of the reset generator to destination 1, flip-flop 40 is noted in the second level. The amount of time that is required from the activation of the reset generator to destination 2, flip-flop 50 is noted in the fourth level. As described above, the differences in times for reset can be attributed to many issues, including longer paths between connection points. The difference in times can be observed wherein the difference time times can be problematic. Moreover, in some instances, as shown in the 4th waveform, which is close to the clock in the 5th waveform, there are instances where a flip-flop arrangement reset may be accomplished in one clock cycle, while another flip-flop arrangement reset may be accomplished in a second clock cycle. The result of this occurrence is that the flip-flops get reset on different clock cycles and unpredictable values may result because of the different resets.
Conventional systems provide for a reset capability within one clock cycle, however these attempts come at a significant cost. The reset capability provides multitudes of connections between different flip-flop architectures with many buffers installed along different paths of the reset tree. The multitude of buffers are created to enable the reset to be roughly synchronous slowing up portions of signals from certain areas so the overall reset can be achieved in a single clock cycle.
In a conventional system, as provided in FIG. 3, signals 300 that are used for reset can be accelerated, thereby causing the signals in some “slow” areas to reach their respective flip-flop arrangements within a single clock signal.
In other conventional systems, as provided in FIG. 4, clocks 400 may be stopped to the destination flip-flop arrangements and then the clocks can be restarted. In an example embodiment, the stopping of clocks 400 then deasserting a reset and then starting of the clocks 400 may be done by software or firmware with multiple instructions.
Such types of conventional systems are costly as firmware code must be added for such controls. Complexity, for example the complexity of the software/firmware, is also increased for such a configuration.
Building buffers for each reset function or building a buffer for a set of reset functions can be quite problematic for chip designers. Chip designers are often limited to specific form factors and deviation from these form factors is generally not allowed. The overall number of flip-flop designs can necessitate a large number of buffers placed on a chip. These buffers can account for a significant area in the plan of the chip, limiting other devices that can be placed on the chip.
It is desired to provide a method and system to provide of system resets to allow for multiple components to be reset at one time without causing system operational issues that happen with conventional systems.
There is also a need to provide a system and method for system resets that is not complicated and that can be used on differing types of systems.